| 基于FPGA技术的DRAM分时存取方法 |
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| 引用本文： | 刘华珠,陈雪芳,黄海云.基于FPGA技术的DRAM分时存取方法[J].现代电子技术,2005,28(10):111-112,115. |
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| 作者姓名： | 刘华珠 陈雪芳 黄海云 |
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| 作者单位： | 1. 东莞理工学院,研究院,广东,东莞,523106
2. 杭州电子科技大学,微电子CAD研究所,浙江,杭州,310018 |
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| 摘 要： | 介绍了一种基于现场可编程技术对DRAM进行读写和刷新操作的方法，根据现场可编程器件设计的特点，结合DRAM读写和刷新时序的要求，提出了同步化操作DRAM的思想，给出了具体同步化操作DRAM的实现方法，针对现场可编程器件设计中经常有多模块同时存取DRAM芯片的需求，提出了对DRAM芯片进行分时存取的方法，讨论了该方法的实现机制，结合具体的项目设计，给出了分时存取方法的关键时序，避开了复杂的DRAM控制器，节省了设计资源，简单方便地解决了DRAM操作的仲裁问题。
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| 关 键 词： | FPGA DRAM 同步化 分时存取方法 |
| 文章编号： | 1004-373X(2005)10-111-02 |
DRAM Time Division Access Method Based on FPGA Technology |
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| LIU Huazhu,CHEN Xuefang,HUANG Haiyun.DRAM Time Division Access Method Based on FPGA Technology[J].Modern Electronic Technique,2005,28(10):111-112,115. |
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| Authors: | LIU Huazhu CHEN Xuefang HUANG Haiyun |
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| Affiliation: | LIU Huazhu 1,CHEN Xuefang 1,HUANG Haiyun 2 |
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| Abstract: | This paper introduces a method to read, write and refresh DRAM chip based on FPGA technology.According to the characteristic of programming device and DRAM read, write and refresh timing sequence, the method to access the DRAM synchronously is discussed in detail.This paper also puts forward a time division access method to solve the multi-modules accessing DRAM problem, and discusses the realization mechanism.With the detailed project design, it introduces the key timing sequence of the time division access method.With this method, it avoids complex DRAM controller, saves the project resource, and solves the DRAM arbitrage problem simply and conveniently. |
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| Keywords: | FPGA DRAM synchronizing time division access method |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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