| 带有P型埋层的新型双栅SOI MOSFET |
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| 引用本文： | 姚国亮,罗小蓉,王琦,蒋永恒,王沛,周坤,吴丽娟,张波,李肇基.带有P型埋层的新型双栅SOI MOSFET[J].半导体学报,2012,33(5):054006-4. |
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| 作者姓名： | 姚国亮 罗小蓉 王琦 蒋永恒 王沛 周坤 吴丽娟 张波 李肇基 |
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| 作者单位： | 电子科技大学电子薄膜与集成器件国家重点实验室,电子科技大学电子薄膜与集成器件国家重点实验室；模拟集成电路重点实验室； |
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| 基金项目： | 国家自然科学基金;国家重点实验室 |
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| 摘 要： | 本文提出一种超低比导通电阻(Ron,sp)可集成的SOI 双栅triple RESURF (reduced surface field)的n型MOSFET (DG T-RESURF)。这种MOSFET具有两个特点：平面栅和拓展槽栅构成的集成双栅结构(DG),以及位于n型漂移区中的P型埋层。首先, DG形成双导电通道并且缩短正向导电路径,降低了比导通电阻。DG结构在反向耐压时起到了纵向场板作用，提高了器件的击穿电压特性。其次, P型埋层形成triple RESURF结构 (T-RESURF),这不仅增加了漂移区的浓度,而且调节了器件的电场。这在降低了比导通电阻的同时提高了击穿电压。最后，与p-body区连接在一起的P埋层和拓展槽栅结构，可以显著降低击穿电压对P型埋层位置的敏感性。通过仿真,DG T-RESURF的击穿电压为325V,比导通电阻为8.6 mΩ?cm2,与平面栅single RESURF MOSFET(PG S-RESURF)相比,DG T-RESURF的比导通电阻下降了63.4%,击穿电压上升9.8%。
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| 关 键 词： | 双栅MOSFET SOI RESURF结构 埋层 P型 表面电场 绝缘体上硅 击穿电压 |
| 收稿时间： | 11/3/2011 2:19:46 PM |
| 修稿时间： | 1/8/2012 2:21:08 PM |
Novel SOI double-gate MOSFET with a P-type buried layer |
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| Yao Guoliang,Luo Xiaorong,Wang Qi,Jiang Yongheng,Wang Pei,Zhou Kun,Wu Lijuan,Zhang Bo and Li Zhaoji.Novel SOI double-gate MOSFET with a P-type buried layer[J].Chinese Journal of Semiconductors,2012,33(5):054006-4. |
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| Authors: | Yao Guoliang Luo Xiaorong Wang Qi Jiang Yongheng Wang Pei Zhou Kun Wu Lijuan Zhang Bo and Li Zhaoji |
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| Affiliation: | State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, China;State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China |
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| Abstract: | |
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| Keywords: | SOI double gates specific on-resistance RESURF breakdown voltage |
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