TP RAM的低功耗优化设计及应用

针对SoC中TP RAM的面积及功耗较大问题，提出一种优化设计方法。通过将SoC中的TP RAM替换成SP RAM，在SP RAM外围增加读写接口转换逻辑，使替换后的RAM实现原TP RAM的功能，保持对外接口不变。为了进一步降低功耗，使用自适应门控时钟，对地址总线进行格雷编码。将文中方法应用于一款多核SoC芯片，该芯片经TSMC 28 nm HPC工艺成功流片，die size为10.5 mm×11.3 mm，功耗为17.07 W。测试结果表明，优化后的RAM面积减少了25.2%，功耗降低了43.07%。

Low power optimization of TP RAM and application

As the area and power consumption of TP RAM in SoC are large, a new design method of optimization is proposed. In order to achieve the function of the original TP RAM and keep the external interface unchanged, TP RAM is replaced with SP RAM, and read-write interface logics of conversion are added around SP RAM. For less power, adaptive clock-gating is used and address bus is encoded through Gray code. The method discussed in this paper is used in the multi core SoC chip which has been successfully taped out in TSMC 28 nm HPC process. The chip occupies 10.5 mm×11.3 mm of die area and consumes 17.07 W. The testing results indicate that the area of optimized RAMs is reduced by 25.2%, and the power saving is 43.07%.