多时钟域的异步信号的参考解决

在ASIC设计中,不同的模块往往工作在不同的频率下,在一个芯片上采用单时钟设计基本上是不可能实现的。多时钟域的设计是SOC设计中的一个重要环节。分析了多时钟域设计中异步信号的产生以及带来的亚稳定性对整个电路性能和功能的影响,提出了采用同步器,握手通信协议,FIFO等方法减小亚稳定性概率和其影响的措施,并且给出了实用电路图并进行了实现,从而使得电路能够在多时钟域下更加健壮和稳定。

Solution of Multi-Asynchronous Clock Design

In ASIC design,different modules often work in different frequency.Designing a pure,one clock synchronous design is luxury and impossible.The multiclock domain design is an important part in SOC.This paper analyses the metastability which is caused by the asynchronous signal flowing in the multiclock domain and puts forward some solutions,for example,using synchronizer,hand shake communication and FIFO to diminish the effect of metastability,so as to make the circuit more stable and robust.The important circuit diagram is proposed for understanding clearly.