一种新式SEU加固PD SOI SRAM单元

本文提出了一种新式SEU加固的10管PD SOI静态存储单元。通过将互锁反相器中的上拉和下拉管分割成两个串联的晶体管，该单元可有效抑制PD SOI晶体管中的寄生BJT和源漏穿通电荷收集效应，这两种电荷收集效应是引起PD SOISRAM翻转的主要原因。通过混合仿真发现，与穿通的浮体6T单元相比，该单元可完全解决粒子入射单个晶体管引起的单粒子翻转。通过分析该新式单元的翻转机制，认为其SEU性能近似与6T SOI SRAM的单粒子多位翻转性能相等。根据参考文献的测试数据，粗略估计该新式单元的SEU性能比普通45nm 6T SOI SRAM单元提升了17倍。由于新增加了四个晶体管，该单元在面积上增加了43.4%的开销，性能方面有所降低。

Novel SEU hardened PD SOI SRAM cell

A novel SEU hardened 10T PD SOI SRAM cell is proposed. By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors, this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOI transistor which causes the SEU in PD SOI SRAM. Mixed-mode simulation shows that this novel cell completely solves the SEU, where the ion affects the single transistor. Through analysis of the upset mechanism of this novel cell, SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references. To achieve this, the new cell adds four transistors and has a 43.4% area overhead and performance penalty.