辐照加固的500MHz锁相环设计

设计了一款与CSMC 0.5μm CMOS工艺兼容的频率为500 MHz的辐照加固整数型锁相环电路,研究了总剂量辐照以及单粒子事件对锁相环电路主要模块及整个系统性能的影响。此外,通过修正BSIM3V3模型的参数以及施加脉冲电流源来模拟总剂量辐照效应和单粒子事件,对锁相环整体电路进行了电路模拟仿真以及版图寄生参数提取后仿真。模拟结果表明,辐照总剂量为1Mrad(Si)时锁相环电路仍能正常工作,产生270.58~451.64 MHz的时钟输出,峰峰值抖动小于100 ps,锁定时间小于4μs;同时在对单粒子事件敏感的数字电路的主要节点处施加脉冲电流源后,锁相环电路均能在短时间内产生稳定的输出。

Design of Radiaiton Hardened 500 MHz Phase-Locked Loop

A radiaiton hardened 500 MHz integer-N PLL was designed using the CSMC 0.5 μm CMOS process.The influences of the total dose radiation and the single event on the main modules of the PLL circuit and the performance of the whole system were investigated.The total dose radiation effects and single event effects were simulated by modifying the parameters of the BSIM 3V3 model and applying the pulse current source.The pre-layout and post-layout simulation result indicts that the circuit can be used to generate 270.58~451.64 MHz clock signal when total dose volume is about 1Mrad(Si).The maximum peak to peak jitter is less than 100 ps while the maximum lock-in time is less than 4 μs.When a pulse current source is exerted in the digital circuits’ nodes of PLL which are sensitive to single event effects,the PLL circuit can still generate a stable output within a short time.