A Circuit Architecture for Analog On-Chip Back Propagation Learning with Local Learning Rate Adaptation

In this paper we present the analog CMOS architecture of a Multi Layer Perceptron network with on-chip stochastic Back Propagation learning. The learning algorithm is based on a local learning rate adaptation technique which makes the on-chip implementation more efficient (i.e. fast convergence speed) with respect to similar architectures presented in the literature. Circuit simulation results on the XOR learning problem validate the network behavior.