A Transistorized Fail-Safe High-Low Trip

The paper describes a novel transistorized trip circuit which was designed according to A.C. fail safe principles, the circuit trips being on high and low levels, thus indicating off normal input conditions. Both levels are detected by a single regenerative comparator. The output decays within 3 msec after a trip condition, independent of input signal slope or level. The circuit posseses an inherent static trip state lock.