8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew |
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Authors: | Jaussi JE Balamurugan G Johnson DR Casper B Martin A Kennedy J Shanbhag N Mooney R |
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Affiliation: | Circuits Res., Intel Labs., Hillsboro, OR, USA; |
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Abstract: | A source-synchronous I/O link with adaptive receiver-side equalization has been implemented in 0.13-/spl mu/m bulk CMOS technology. The transceiver is optimized for small area (360 /spl mu/m /spl times/ 360 /spl mu/m) and low power (280 mW). The analog equalizer is implemented as an 8-way interleaved, 4-tap discrete-time linear filter. The equalization improved the data rate of a 102 cm backplane interconnect by 110%. On-die adaptive logic determines optimal receiver settings through comparator offset cancellation, data alignment of the transmitter and receiver, clock de-skew and setting filter coefficients for equalization. The noise-margin degradation due to statistical variation in converged coefficient values was less than 3%. |
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