一种高性能9/7离散小波变换滤波器的硬件设计

基于提升格式的离散小波变换比传统的基于卷积的运算量少，易于VLSI实现。本文提出了一种基于提升格式，高效实时实现JPEG2000中9/7双正交离散小波变换滤波器的VLSI结构设计方法。该方法所设计的结构，在保证同样的精度下，减少了运算量，整体运算速度高，硬件花费少，存储需求低，硬件利用率达到100%。本文用Verilog HDL对系统进行硬件描述，并选用Xilinx公司的XCV50e-cs144-8器件在ISE4.1环境下实现了综合。

Hardware Design of a High-Performance 9/7 DWT Filter

The discrete wavelet transform（DWT） based on lifting scheme requires far fewer computations than convolution-based DWT and can be applied to VLSI better. A high-efficient, real-time VLSI architecture is proposed that can perform 9/7 biorthogonal diserete wavelet transform （ DWT ） in JPEG 2000. By using this architecture , the computations are reduced enormously with the same precision , the whole computation speed is high with less hardware cost and low memory requirement , this architecture can achieve 100% hardware utilization. The algorithm is described and simulated by Verilog HDL, which is then synthesized by XCV50ecs144-8 under Xilinxs＇ISE4. 1.