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Analog Circuit Design Methodology in a Low Power RISC Microprocessor
Authors:Koichiro Ishibashi  Hisayuki Higuchi  Toshinobu Shimbo  Kunio Uchiyama  Kenji Shiozawa  Naotaka Hashimoto  Shuji Ikeda
Affiliation:(1) Central Research Laboratory, Hitachi Ltd., Kokubunji-shi, 185-8601, Japan;(2) Hitachi ULSI Corporation, Kokubunji-shi, 185-0014, Japan;(3) Semiconductor and LSI Division, Hitachi Ltd., Kodaira-shi, 187-0022, Japan
Abstract:There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96-mm2 test chip with the super H architecture using 0.35-mgrm four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2.0-W power dissipation.
Keywords:microprocessor  TLB  CAM  0  35 mgrm" target="_blank">gif" alt="mgr" align="MIDDLE" BORDER="0">m  CMOS
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