数字化变电站合并单元自动误差校验技术及应用

合并单元的准确性直接影响数字化变电站甚至智能电网的安全稳定运行。为此，从硬件设计和算法研究两方面着手提升合并单元误差校验准确度和实时性，详细给出了合并单元校验系统硬件设计原理，提出了基于最小旁瓣卷积窗的频谱相位校正算法，实现了合并单元比差和角差准确估计，建立了合并单元时钟误差校验方案，实现了时钟误差校验、守时功能测试和绝对延时计算。实验结果证明了本文设计的数字化变电站合并单元自动误差校验系统运行稳定可靠，满足实际测量需求。

Merging unit automatic error verification technology and its application in digital substation

The accuracy of the merging unit directly affects the safe and stable operation of digital substations and even smart grids. For this reason, the accuracy and real-time performance of the merging unit error check are improved from the aspects of hardware design and algorithm research. The hardware design principle of the merging unit check system is given in detail, and the spectrum phase correction based on the minimum side lobe convolution window is proposed. The algorithm realizes the accurate estimation of the unit difference and angular difference of the merging unit, establishes the merging unit clock error check scheme, and realizes the clock error check, punctual function test and absolute delay calculation. The experimental results show that the digital substation merging unit automatic error checking system designed in this paper runs stably and reliably, and meets the actual measurement requirements..