基于扫描的VLSI全速测试方法

当工艺进入到超深亚微米以下,传统的故障模型不再适用,必须对电路传输延迟引发的故障采用延迟故障模型进行全速测试.给出了常用的延迟故障模型,介绍了一种基于扫描的全速测试方法,并给出了全速测试中片上时钟控制器的电路实现方案.对芯片进行测试,可以直接利用片内锁相环电路输出的高速时钟对电路施加激励和捕获响应,而测试向量的扫描输入和响应扫描输出则可以采用测试机提供的低速时钟,从而降低了全速测试对测试机时钟频率的要求.最后,对于全速测试方案提出了若干建议.

Scan-Based At-Speed Test for VLSI

As the VLSI technology scales down to deep sub-micro, traditional default models are not available any more. It is necessary to adopt delay default models and implement at-speed test for the faults caused by circuit propagation delay. Delay fault models in common use were described and a scan-based atspeed test method was introduced. Following this method, the on-chip clock could be directly used as the atspeed clock during launch and capture phase while the ATE clock was only used during shift phase, so that atspeed test can be implemented with a low speed ATE. The circuitry implementation of the on-chip clock controller used in at-speed test was also introduced. Finally, some suggestions were made on at-speed test schemes.