Modeling of tunneling P/E for nanocrystal memories |
| |
Authors: | Compagnoni CM Ielmini D Spinelli AS Lacaita AL |
| |
Affiliation: | Dipt. di Elettronica. e Informazione, Politecnico di Milano, Milan, Italy; |
| |
Abstract: | This paper presents a detailed study of the program/erase (P/E) dynamics under uniform tunneling for nanocrystal (NC) memories. Calculating the potential profile and the tunneling currents across the dielectric barriers, we evaluate NC charging and discharging transients during P/E operations. The calculated P/E windows and times compare well with experimental data for memory cells with different oxide thicknesses. The model accounts for the typical features of threshold voltage (V/sub T/) shift as a function of applied gate voltage, and can be used as a valuable tool for optimizing the cell geometry and parameters for maximum performance. |
| |
Keywords: | |
|
|