H.264解码中反变换的硬件实现及仿真

新一代视频编码标准H．264为了提高编码效率而采用了一系列新技术，而新技术的使用也极大增加了算法的复杂度。针对目前视频解码时采用软件方法对CPU资源占有率过高的问题，提出了一种用硬件＋微代码的方式实现解码中整数IDCT变换的设计方案。对设计结果，进行了功能和时序的仿真，证明了设计方案的正确性及可行性。在硬件主频大于150MHz时，完全可以对视频进行实时解码。从而提供了一套可供参考的对视频解码算法进行优化及仿真验证的方法。

Implementation & Simulation of Inverse Transform of H. 264 Decoding-Hardware

New generation video encoding standard H. 264 achieves high coding efficiency through adding new features and functionalities. However, these new features and functionalities greatly increase the complexity in encoding and decoding. Aiming at the problem that using software for video decoding results in occupying a high percentage of CPU resource, this paper implements the integer inverse transform within H. 264 decoding process using hardware and microcode. Simulation software for functional verification and RTL code for front - end timing simulation are available for the design to prove its correctness and feasibility. With a frequency higher than 150MHz, the hardware unit is totally capable of processing real - time video decoding, Thus, this paper presents a method to optimize and verify H. 264 video decoding algorithm.