A 6-Gbps dual-mode digital clock and data recovery circuit in a 65-nm CMOS technology期刊界 All Journals 搜尽天下杂志传播学术成果专业期刊搜索期刊信息化学术搜索

A 6-Gbps dual-mode digital clock and data recovery circuit in a 65-nm CMOS technology

Authors:	Min-Ki Jeon Changsik Yoo

Affiliation:	1. Integrated Circuits Laboratory, Department of Electronic Engineering, Hanyang University, Seoul, 133-791, Korea

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