Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP

The integrated circuit industry not only demands finding optimal design solutions over an efficient process, but also requires the address of increased reliability challenges, caused by strong electric fields, to elevate the overall system robustness. This work reconciles such an inconsistency by proposing a transistor-level methodology for current steering DACs to map their specs onto transistor sizes and improve their performance, parametric yield as well as lifetime reliability through the state of the art evolutionary tools and reliability simulator. The tradeoff between performance specs and power consumption is obtained through a multi-objective approach by considering process variations together with lifetime stress effects. The 10-bit DAC@130MS/s is herein implemented using TSMC CMOS 0.18 μm technology. Demonstrated results point out optimal design points in short and long time reliability as well as performance parameters over a computational effective procedure.