A low-power low-jitter DLL with a differential closed-loop duty cycle corrector

This paper presents an optimization-based design methodology for fully differential amplifiers (FDAs) including the effects of real common-mode feedback (CMFB) circuits as constraints in the design flow. The sizing procedure is performed separately for the main amplifier and for the CMFB circuit, reducing the number of free variables and exploring the design space in a more efficient way. Also, this methodology can be employed to design single and two-stages FDAs whereas a second pole compensation scheme is necessary. In order to validate the proposed methodology, a two-stage fully differential amplifier with a no capacitor feed-forward (NCFF) compensation technique was designed in 0.13 μm CMOS technology with a 1.2 V power supply. The presented results also include a pole-zero pair mismatch analysis and proposes a solution in order to compensate the generated pole-zero doublet that might affect the performance of the amplifier. We can show that this approach reduces the overall static power consumption while satisfying the design specifications.