| 槽栅型肖特基势垒静电感应晶体管 |
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| 引用本文： | 杨涛,刘肃,李思渊,王永顺,李海蓉. 槽栅型肖特基势垒静电感应晶体管[J]. 半导体技术, 2008, 33(1): 65-67 |
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| 作者姓名： | 杨涛 刘肃 李思渊 王永顺 李海蓉 |
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| 作者单位： | 兰州大学,物理科学与技术学院,微电子学研究所,兰州,730000;兰州交通大学,电子与信息工程学院,电子科学与技术系,兰州,730070 |
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| 摘 要： | 传统的静电感应晶体管多采用扩硼的方法制备栅极区,这种工艺热预算较高,使得工艺复杂程度和生产成本较高,基于此提出并设计了一种新型的槽栅型肖特基势垒静电感应晶体管.使用V形槽工艺,用溅射铝的方法代替扩硼工艺制备静电感应晶体管的栅极区,简化了工艺流程,使器件在调试过程中具有很大灵活性.使用PECVD(等离子体增强化学气相淀积)工艺,解决了槽栅结构静电感应晶体管的栅极区与源极区容易短路的问题.给出了详细的工艺流程.
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| 关 键 词： | 静电感应晶体管 V形槽 等离子体增强化学气相淀积 肖特基势垒 |
| 文章编号： | 1003-353X（2008）01-0065-03 |
| 收稿时间： | 2007-09-04 |
| 修稿时间： | 2007-09-04 |
V-Groove Recessed-Gate Schottky Barrier Static Induction Transistor |
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| Yang Tao,Liu Su,Li Siyuan,Wang Yongshun,Li Hairong. V-Groove Recessed-Gate Schottky Barrier Static Induction Transistor[J]. Semiconductor Technology, 2008, 33(1): 65-67 |
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| Authors: | Yang Tao Liu Su Li Siyuan Wang Yongshun Li Hairong |
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| Affiliation: | Yang Tao1,Liu Su1,Li Siyuan1,Wang Yongshun2,Li Hairong1(1.Institute of Microelectronics,School of Phys.Science , Tech.,Lanzhou University,Lanzhou 730000,China,2.School of Electronic , Information Engineering,Lanzhou Jiaotong University,Lanzhou 730070,China) |
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| Abstract: | The gate region of conventional SIT(static induction transistor)is usually prepared by B diffusion in n-type Si,the preparation is complex and high in cost,so a new recessed-gate Schottky barrier SIT was proposed.The gate region was fabricated by V-groove and Al sputtering,which can simplify the process,and make devices flexible in the adjustment process.By PECVD the short circuit problem between the source region and the gate region in recessed-gate SIT can be avoid.The main steps for process were given. |
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| Keywords: | SIT V-groove plasma enhanced chemical vapor deposition(PECVD) Schottky barrier |
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