| 一种有限域快速低功耗模乘电路设计与实现 |
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| 引用本文： | 程桂花,罗永龙,齐学梅,左开中.一种有限域快速低功耗模乘电路设计与实现[J].计算机时代,2012(4):21-23. |
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| 作者姓名： | 程桂花 罗永龙 齐学梅 左开中 |
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| 作者单位： | 安徽师范大学数学计算机科学学院,安徽芜湖241000;安徽师范大学网络与信息安全工程技术研究中心 |
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| 基金项目： | 国家自然基金（60703071）; 安徽省优秀青年科技基金项目（08040106806）; 安徽省自然科学基金（070412043） |
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| 摘 要： | 有限域的运算是密码学的基础,而在有限域的运算中模乘运算是核心运算之一。为此,分析了模乘运算的原理及特点,使用Verilog HDL设计模乘电路,通过FPGA实现了基于有限域的模乘运算。电路应用双沿寄存器结构,并且规模小、速度快、功耗低能实现有限域通用模乘运算对加密算法的硬件实现具有实际价值。
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| 关 键 词： | 有限域 模乘 模2运算 硬件设计 |
Design and implementation of a modular multiplication circuit of low power and high speed |
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| Cheng Guihua
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Luo Yonglong
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Qi Xuemei
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Zuo Kaizhong.Design and implementation of a modular multiplication circuit of low power and high speed[J].Computer Era,2012(4):21-23. |
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| Authors: | Cheng Guihua Luo Yonglong Qi Xuemei Zuo Kaizhong |
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| Affiliation: | 1. College of Mathematics and Computer Science, Anhui Normal University, Wuhu, Anhui 241000, China; 2. Research Center of Network and Information Security, Anhui Normal University, Anhui Normal University) |
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| Abstract: | The finite field arithmetic is the base of cryptography and modular multiplication is one of core operations. Based on analysis of finite field modular multiplication, the authors design a modular multiplication circuit in Verilog HDL, and its modular multiplication is realized by FPGA in finite fields. The circuit uses double-edge-triggered register, and realizes small-scale, low power consumption and high speed. It implements modular multiplication to reduce its scale and it has practical value for hardware implementation of encoding algorithm. |
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| Keywords: | finite fields modular multiplication modular 2 arithmetic hardware design |
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