| 多码率QC-LDPC译码器设计与实现 |
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| 引用本文： | 陈赟,陈翔,赵明,王京. 多码率QC-LDPC译码器设计与实现[J]. 通信技术, 2011, 44(2): 34-35,38 |
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| 作者姓名： | 陈赟 陈翔 赵明 王京 |
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| 作者单位： | 1. 厦门大学,信息科学与技术学院,福建,厦门,361000
2. 清华大学信息技术研究院,北京,100084 |
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| 摘 要： | 低密度奇偶校验码（LDPC）是目前最有效的差错控制手段之一,而其中准循环LDPC码（QC-LDPC）应用最为广泛。提出了一种通用的多码率QC-LDPC译码器设计方法,并在FPGA上完成了实现和测试。测试结果表明,该多码率译码器在资源占用不超过2种码率译码器资源之和的前提下能够有效支持至少3种码率;且工作时钟在110 MHZ时,固定迭代次数为16次,该译码器的吞吐率能保持在110 Mb/s以上。
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| 关 键 词： | 多码率 QC-LDPC译码器 偏移值最小和算法 现场可编程门阵列 |
Design and Implementation of Multi-rate QC-LDPC Decoder |
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| CHEN Yun,CHEN Xiang,ZHAO Ming,WANG Jing. Design and Implementation of Multi-rate QC-LDPC Decoder[J]. Communications Technology, 2011, 44(2): 34-35,38 |
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| Authors: | CHEN Yun CHEN Xiang ZHAO Ming WANG Jing |
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| Affiliation: | ②(①College of Information Science and Technology,Xiamen University,Xiamen Fujian 361000,China; ②Research Institute of Information Technology,Tsinghua University,Beijing 100084,China) |
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| Abstract: | Low-density parity-check(LDPC) code is one of the most effective error-controlling methods,in which the quasi-cyclic(QC) LDPC code is the most popular class.This paper proposes a design method for multi-rate QC-LDPC decoder,and then describes the implementation and test on FPGA.The test results show that the resource occupied by the multi-rate decoder is not more than two times of the resource occupied by the single-rate decoder,and this multi-rate decoder could support at least 3 code rates with the throug... |
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| Keywords: | multi-rate QC-LDPC decoder offset min-sum algorithm FPGA |
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