高速并行数字调制信号的产生与实现

数字调制技术是高速通信传输系统的关键技术之一。本文提出了一种全并行的高速数字调制信号产生架构，该架构可以在现场可编程门阵列(FPGA)硬件平台中通过算法级的流水线实现。通过理论分析与推导，并行频域成型滤波器中的DFT/IDFT可以由低复杂度的两个基-8 FFT算法级联构成，进一步给出了具体的FPGA架构和实现方法。另外，为了进一步降低硬件资源，本文分析并设计了一种适用于并行实现的免混频数字正交上变频架构。仿真实验对高速并行数字调制架构中的并行频域成型滤波器在时域和频域分别进行了算法验证，FPGA硬件实现结果验证了高速并行数字调制信号产生的频谱性能。

Generation and implementation of high-speed parallel digital modulation signals

Digital modulation technology is one of the key technologies of the high-speed communication transmission system. In this article, an architecture of high-speed digital modulation signal generation in parallel is proposed, which can be implemented by algorithm-level pipeline in field programmable gate array (FPGA) hardware platform. With theoretical analysis and derivation, DFT/ IDFT in parallel frequency domain forming filter can be cascaded by two levels of the low-complexity based-8 FFT algorithm, and the specific FPGA architecture and implementation method are given. In addition, a mixing-free digital orthogonal up-conversion architecture suitable for parallel implementation is analyzed and designed to further reduce hardware resource. The simulation experiments evaluate the algorithm of the high-speed parallel digital modulation architecture, and the FPGA hardware implementation results test the spectrum performance of the high-speed parallel digital modulation signal.