Fault Modeling and Simulation Using VHDL-AMS |
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Authors: | A J Perkins M Zwolinski C D Chalk B R Wilkins |
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Affiliation: | (1) Department of Electronics and Computer Science, University of Southampton, Southampton, SO17 1BJ, UK |
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Abstract: | Fault simulation is an accepted part of the test generation procedure for digital circuits. With complex analog and mixed-signal integrated circuits, such techniques must now be extended. Analog simulation is slow and fault simulation can be prohibitively expensive because of the large number of potential faults. We describe how the number of faults to be simulated in an analog circuit can be reduced by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks. These behavioral models can be implemented in SPICE or in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS does potentially offer advantages in tackling this problem, but there are a number of computational difficulties to be overcome. |
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Keywords: | analog simulation analog test fault simulation fault modeling analog VHDL |
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