Design and implementation of an all-CMOS 802.11a wireless LAN chipset

The tremendous growth in wireless LANs has generated interest in technologies that provide higher data rates and greater system capacities. The IEEE 802.11a standard, based on coded OFDM modulation, provides nearly five times the data rate and at least 20 times the overall system capacity compared to the incumbent 802.11b wireless LAN systems. This article describes the design challenges and circuit implementation of a two-chip set that forms a complete 802.11a solution in 0.25 /spl mu/m CMOS technology. Wherever possible, sophisticated digital signal processing techniques are used to compensate for possible analog impairments associated with integrating RF circuitry in a CMOS technology. The analog portion of the chip set implements a 5 GHz transceiver comprising all the necessary RF and analog circuits of the 802.11a standard integrated on a single chip. Some features of this IC include 22 dBm peak transmitted power, 8 dB overall receive-chain noise figure, and -112 dBc/Hz synthesizer phase noise at 1 MHz frequency offset. The digital portion of the chip set, the baseband and MAC processor, contains dual ADCs/DACs and all the digital circuits for synchronization, detection, and 802.11 MAC layer data processing. This IC delivers up to 54 Mb/s in a 20 MHz channel according to the 802.11a standard, and includes proprietary modes supporting up to 108 Mb/s in a 40 MHz channel.