Hybrid cascode compensation with feedforward stage for high-speed area-efficient three-stage CMOS amplifiers

Hybrid cascode feedforward compensation (HCFC) is proposed for low-power area-efficient three stage amplifiers driving large capacitive loads. With no overhead in power or area, the total compensation capacitor is divided and shared between two internal high-speed loops instead of solely one loop as is common in prior art. Detailed analysis of HCFC shows significant improvement in terms of stability and bandwidth. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30 and 40 %, respectively, compared to the prevailing schemes.