CMOS logic gate performance variability related to transistor network arrangements |
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Authors: | Digeorgia N. da Silva, Andr I. Reis,Renato P. Ribas |
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Affiliation: | aPPGMicroelectronics – Federal University of Rio Grande do Sul, Av. Bento Gonçalves 9500, CEP 91501-970, Porto Alegre, RS, Brazil |
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Abstract: | The rapid scaling of CMOS technology has resulted in drastic variations of process parameters. Since different transistor arrangements present different electrical characteristics, this work analyzes the impact of process variability in performance of logic gates, according to their topology and the relative position of the switching device in the network. Results have been obtained through Monte-Carlo simulations and design guidelines for parametric yield improvement have been derived. |
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