适用于12 bit流水线ADC采样保持电路的设计

介绍了一种用于12 bit,20 MS/s流水线模数转换器前端的高性能采样/保持电路。该电路采用全差分结构、底极板采样来消除电荷注入和时钟馈通误差。采用栅压自举开关,并通过对电路中的开关进行组合优化,极大地提高了电路的线性性能。同时,运算放大器采用折叠式增益增强结构,以获得较高的增益和带宽。采用CSMC公司的0.5μm CMOS工艺库,对电路进行了仿真和流片。结果表明,在5 V电源电压下,采样频率为20 MHz,采样精度可达到0.012%,在输入信号为奈奎斯特频率时,无杂散动态范围(SFDR)为76 dB。

Design of Sample and Hold Circuit for 12 bit Pipelined ADC

A high performance CMOS sample and hold (S/H) circuit used in a 12 bit 20 MS/s ADC is presented.Fully differential circuit and bottom-plate sampling were used to eliminate both charge injection and clock feed through error.Using bootstrapped switches and optimizing the switches arrangement,the linearity was improved.A fully differential folded cascade operational amplifier was designed using a gain booster circuit in order to get high-gain.wideband and reduce the power consumption.The circuit was simulated and taped out based on 0.5 μm CMOS process CSMC.Simulation results show that it achieves a precision of 0.012% and a SFDR of 76 dB when working at a Nyquist input signal and 5V supply voltage.