Interfacial delamination investigation between copper bumps in 3D chip stacking package by using the modified virtual crack closure technique |
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Authors: | C.J. Wu M.C. HsiehC.C. Chiu M.C. Yew K.N. Chiang |
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Affiliation: | a Advanced Packaging Research Center, National Tsing Hua University, Taiwan b Department of Power Mechanical Engineering, National Tsing Hua University, Taiwan c Electronics and Optoelectronics Research Laboratories (EOL)/Industrial Technology Research Institute (ITRI), Taiwan |
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Abstract: | In this study, the modified virtual crack closure technique (MVCCT) incorporated with the finite element method (FEM) is applied to investigate the delamination behavior between stacked copper bumps in 3D chip stacking packaging at package-level and board-level, and the energy release rate at the delamination front is evaluated as the criterion of the crack expansion. The package-level structure is firstly simulated to validate the dependability of MVCCT, and the results reveal that the delamination between copper bumps within specific size will not induce delamination expansion during thermal cycling condition, which show good agreement with experiment results. The mesh density and the delamination geometry effect analyses are also studied at package-level to ensure the reliable result of finite element analysis. The results show that the former has an insignificant effect on the energy release rate, while the later has a significant influence. Moreover, based on the simulation results at package-level structure, the further delamination behavior at board-level is investigated to predict potential failure mode different from the package-level structure. The results show higher energy release rate is induced and mixed fracture mode occurs. |
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Keywords: | Chip stacking 3D package Copper bump MVCCT FEM |
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