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Characterization and modeling of RF substrate coupling effects in 3D integrated circuit stacking |
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| Authors: | E. Eid,T. LacrevazC. Bermond,S. CapraroJ. Roullard,B. Flé chetL. Cadix,A. FarcyP. Ancey,F. CalmonO. Valorge,P. Leduc |
| Affiliation: | a Université de Savoie, IMEP-LAHC, UMR CNRS 5130, 73376 Le Bourget du Lac Cedex, France b STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France c Institut des Nanotechnologies de Lyon, INSA, UMR CNRS 5270, 69621 Villeurbanne, France d CEA-LETI, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France |
| Abstract: | This work addresses parasitic substrate coupling effects in 3D integrated circuits due to Through Silicon Vias (TSV). Electrical characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling phenomena when RF signals are propagated in TSV. A good compatibility between RF measurements and RF simulations allows validating modeling tools for predictive studies. Next, parametric studies are performed in order to study impact of TSV design and materials on substrate coupling noise. |
| Keywords: | 3D integration Silicon substrate Through Silicon Vias (TSV) Capacitive, conductive and inductive coupling Microwave |
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