Interconnect reliability - A study of the effect of dimensional and porosity scaling

A number of challenges linked to the reliability characterization of downscaled back-end-of-line copper/low-k interconnects are covered. Concerning copper reliability, it is shown using early data on 30 nm ½pitch that advanced barrier/seed/plating options can counteract models that predict decreased electromigration performance in smaller dimensions. Regarding stress-induced voiding, it is discussed that porosity scaling negatively influences metal degradation due to increased stress gradients. Also, since copper degradation during high temperature storage tests is driven by different failure mechanisms, it is argued that tests at a wide range of temperatures are needed to characterize stress-induced voiding in copper/low-k systems at normal operating conditions. In addition, it is suggested that the current knowledge on the dependence of interconnect pitches and dielectric porosity on stress in copper lines needs to be taken into account when building finite element models of copper/low-k stacks. This is motivated by highlighting results of our recent study where the copper strain is varied for different copper dimensions and pattern densities. Finally, because the reliability margin of time dependent dielectric breakdown of scaled intermetal dielectrics becomes smaller, it is put forward that understanding the low voltage behaviour of time dependent dielectric breakdown becomes indispensable. A case study using fully passivated MOS capacitors without metallic barrier between the copper and the dielectric is detailed out and differences in current versus time behaviour and distributional shapes between low and high fields are highlighted.