首页 | 本学科首页   官方微博 | 高级检索  
     


Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration
Authors:Chung-Chieh KuoAuthor VitaeChia-Chun TsaiAuthor Vitae  Trong-Yen LeeAuthor Vitae
Affiliation:a Department of Computer Science and Information Engineering, Nanhua University, Chiayi, Taiwan
b Graduate Institute of Computer and Communication, National Taipei University of Technology, Taipei, Taiwan
Abstract:As IC fabrication technologies get into nanometer era, clock routing gradually dominates chip performance indicated by delay, cost, and power consumption. X-architecture can be applied for routing metal wires in diagonal and rectilinear directions to overcome the above challenges due to wirelength reduction. In this paper, we present a clock routing algorithm, called PMXF, to construct an X-architecture zero-skew clock tree with minimum delay. An X-pattern library is defined for simplifying the merging procedure of the DME approach, an X-Flip technique is proposed for reducing the wirelength between the paired points, and a wire sizing technique is applied for achieving zero skew. In terms of clock delay, wirelength, power consumption, and via count listed in the experimental results on benchmarks, the proposed PMXF algorithm can respectively achieve more reductions compared with other previous X-architecture clock routing algorithms.
Keywords:Zero-skew clock routing  Interconnect delay  Pattern matching  X-architecture
本文献已被 ScienceDirect 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号