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Integration challenges of copper Through Silicon Via (TSV) metallization for 3D-stacked IC integration |
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| Authors: | J. Van Olmen C. HuyghebaertJ. Coenen J. Van AelstE. Sleeckx A. Van AmmelS. Armini G. Katti J. VaesW. Dehaene E. BeyneY. Travaly |
| Affiliation: | a IMEC VZW, Kapeldreef 75, B-3001 Leuven, Belgium b EE Department, K.U. Leuven, Kasteelpark Arenberg 10, Leuven B-3001, Belgium |
| Abstract: | In this paper we will highlight key integration issues that were encountered during the development of the 3D-stacked IC Through Silicon Via (TSV) module and present solutions to achieve a robust copper TSV. Electrical performance of the obtained TSV module is discussed based on a lumped RC model for 3D ring oscillators containing TSVs between bottom and top tiers. |
| Keywords: | Through Silicon Via (TSV) 3D integration Metallization |
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