MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate |
| |
Authors: | Yung-Hsien Wu Lun-Lun ChenWei-Chia Chen Chia-Chun LinMin-Lin Wu Jia-Rong Wu |
| |
Affiliation: | Department of Engineering and System Science, National Tsing Hua University, Hsinchu 30013, Taiwan |
| |
Abstract: | A Ge-stabilized tetragonal ZrO2 (t-ZrO2) film with permittivity (κ) of 36.2 was formed by depositing a ZrO2/Ge/ZrO2 laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO2. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO2 gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH3 plasma, good leakage current of 4.8 × 10−8 A/cm2 at Vg = Vfb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained. |
| |
Keywords: | High-κ gate dielectric Ge-stabilized tetragonal ZrO2 ZrO2/Ge/ZrO2 laminate NH3 plasma nitridation |
本文献已被 ScienceDirect 等数据库收录! |