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Optimization of gate stack parameters towards 3D-SONOS application |
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| Authors: | L Breuil G Van den boschA Cacciato L DateGS Kar B Tang A ArreghiniI Debusschere J Van Houdt |
| Affiliation: | a IMEC, Kapeldreef 75, Leuven, Belgium b Applied Materials Belgium, Kapeldreef 75, Leuven, Belgium c Liverpool John Moores University, 2 Rodney street, Liverpool, UK |
| Abstract: | A planar SONOS capacitor was used to optimize different parameters of the gate stack, in view of integration in a 3D cell. It is found that a poly-Si substrate strongly degrades the channel mobility but program and retention are not compromised. The ONO stack is found to scale down to 3/4/5 nm for tunnel oxide/trapping nitride/blocking oxide, respectively. FUSI gate could be an interesting option to improve the erase operation. |
| Keywords: | Charge trapping memory SONOS Thin film substrate FUSI |
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