| Abstract: | As pressures increase on VLSI designers to use a lower supply voltage of 3.3 V rather than the present 5 V, current mode signal-processing techniques will surely become increasingly important and attractive. This paper presents the design of a reference-generating (RG) circuit which employs a current mode divide-by-two circuit. Current dividers are usually implemented by using resistor networks or weighted transistors. the division accuracy of such solutions is limited by resistor or transistor mismatch. In this study the proposed divide-by-two circuit does not rely on well-matched components and high-gain op amps to achieve high accuracy. This paper also addresses the relationship among the operation and accuracy of the division process, the transistor mismatch and the resolution of a converter which employs the RG circuit. the proposed RG circuit can be implemented not only for medium-speed successive approximation current mode A/D converters but also for A/D converter arrays achieving a high conversion rate. |
