Self-aligned silicon-on-insulator nano flash memory device

This paper reports on the fabrication of a silicon-on-insulator nano flash memory device based on the differential oxidation rate of silicon resulting from gradients in the arsenic doping concentration. The key processes involved are the formation of the desired arsenic doping profile, electron beam lithography and wet oxidation. The resulting device is a triangular-channel MOSFET with a nanocrystal floating gate embedded in the gate oxide. The length, width and height of the nanocrystal are 10, 10 and 20 nm, respectively. As long as the control gate voltage does not exceed ±2V, the device behaves like a thin and narrow P-channel MOSFET. When a voltage of −5 or +5 V is applied to the control gate at room temperature, holes are injected into the floating gate or removed from it, respectively. This effect induces a persistent shift of the threshold voltage of the device, which acts as a miniature EEPROM.