A reconfigurable processor architecture combining multi-core and reconfigurable processing units |
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Authors: | Like Yan Binbin Wu Yuan Wen Shaobin Zhang Tianzhou Chen |
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Affiliation: | 1. College of Computer Science, Zhejiang University, Hangzhou, P.R. China 2. Samsung Semiconductor China Research Centre, Hangzhou, P.R. China
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Abstract: | It’s a promising way to improve performance significantly by adding reconfigurable processing unit (RPU) to a general purpose processor. In this paper, a Reconfigurable Multi-Core (RMC) architecture combining general multi-core and reconfigurable logic is proposed. Reconfigurable logic is separated into RPUs logically, which are coupled with general purpose cores as co-processors via a full crossbar switch. An RPU Manager (RPU-M) is also designed to manage RPUs. To verify RMC, a simulation method based on the Simics and Virtex 5 FPGA is adopted, which simplifies the simulation and assures the evaluation accuracy of hardware function cores. Five workloads are selected to test RMC, including 3-DES, AES, SHA2, IDCT and JPEG_ENC. The experimental results show a 3.10 times average speedup over software implementation on the original multi-core, and the data and control communication overhead on RMC is acceptable. |
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