| GEDS中的联机增量式设计规则检查及其实现 |
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| 引用本文： | 应昌胜,洪先龙,王尔乾.GEDS中的联机增量式设计规则检查及其实现[J].半导体学报,1991,12(2):108-113. |
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| 作者姓名： | 应昌胜 洪先龙 王尔乾 |
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| 作者单位： | 清华大学计算机系 北京100084
(应昌胜,洪先龙),清华大学计算机系 北京100084(王尔乾) |
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| 摘 要： | 版图的联机增量式设计规则检查(IDRC)是指在版图设计过程中随设计的进行渐进完成版图设计规则检查.我们在版图交互编辑系统GEDS中嵌入并实现了一个IDRC过程.文中介绍了基本的设计规则检查算法和IDRC的实现策略.结合版图的分级设计还讨论了分级设计规则检查方法.
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| 关 键 词： | CAD 集成电路 版图设计 规则检查 |
An On-Line Incremental Design Rule Checker in GEDS |
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| Ying Changsheng/.An On-Line Incremental Design Rule Checker in GEDS[J].Chinese Journal of Semiconductors,1991,12(2):108-113. |
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| Authors: | Ying Changsheng/ |
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| Affiliation: | Ying Changsheng/Department of Computer Science and Technology,Tsinghua University,BeijingHong Xianlong/Department of Computer Science and Technology,Tsinghua University,BeijingWang Erqian/Department of Computer Science and Technology,Tsinghua University,Beijing |
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| Abstract: | A new technique of on-line incremental design rule checking "IDRC" is presented.Itchecks violations of the design rules in accompany with the interactive mask layout design andreports the errors immediately whenever they are detected. We have embedded an IDRC routineinto a layout editor named GEDS. The algorithms for basic operations of design rule check-ing are described. The scheme for the hierarchically constructed layout design is also discus-sed. |
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| Keywords: | Design rule checking Layout design CAD |
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