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基于FPGA的DDR控制器的实现
引用本文:郑佳,李永亮,李娜.基于FPGA的DDR控制器的实现[J].无线电工程,2007,37(10):23-25.
作者姓名:郑佳  李永亮  李娜
作者单位:中国人民解放军61541部队,北京,100094
摘    要:目前,DDR SDRAM因其拥有比SDRAM双倍的数据速率,已经成为存储器的主流,得到了广泛应用。使用Altera公司的Cyclone FPGA芯片设计实现了一个DDR控制器,为微控制器或数字信号处理器与DDR SDRAM之间连接提供了一种方案。详细叙述了其基本结构和设计思想,并给出了DDR控制器的状态转换图和在设计与实现中应注意的几个问题。

关 键 词:DDR  SDRAM  FPGA  PLLs
文章编号:1003-3106(2007)10-0023-03
修稿时间:2007-05-16

Implementation of DDR Controller Based on FPGA
ZHENG Jia,LI Yong-liang,LI Na.Implementation of DDR Controller Based on FPGA[J].Radio Engineering of China,2007,37(10):23-25.
Authors:ZHENG Jia  LI Yong-liang  LI Na
Affiliation:61541 Unit of PLA , Beijing 100094, China
Abstract:The DDR SDRAM has been used extensively and become the main product of memory because of its double-data-rata at present.In this paper,we designed and completed a DDR controller by using the Cyclone FPGA device produced by the Altera Corporation,which offered one way to connect the Micro-controller or DSPs with the DDR SDRAM,The main structures and design ideas of a DDR controller are described in detail,and a state switching map is presented in this paper.Finally,some issues on design and implementation are given.The result shows the feasibility of design.
Keywords:DDR SDRAM  FPGA  PLLs
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