A threshold-voltage model of SiGe-channel pMOSFET without Si cap layer |
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| Authors: | X Zou JP Xu CX Li PT Lai WB Chen |
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| Affiliation: | aDepartment of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, People’s Republic of China;bDepartment of Electrical and Electronic Engineering, The University of Hong Kong, Pokfulam Road, Hong Kong, China |
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| Abstract: | An analytical model on the threshold voltage of SiGe-channel pMOSFET with high-κ gate dielectric is developed by solving the Poisson’s equation. Energy-band offset induced by SiGe strained layer, short-channel effect and drain-induced barrier lowering effect are taken into account in the model. To evaluate the validity of the model, simulated results are compared with experimental data, and good agreements are obtained. This model can be used for the design of SiGe-channel pMOSFET, thus determining its optimal parameters. |
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