基于与非锥的新型FPGA逻辑簇互连结构研究

该文针对新型FPGA可编程逻辑单元与非锥(And-Inverter Cone, AIC)的结构特性，提出一系列方案以得到优化的逻辑簇互连结构，包括:移除输出级交叉矩阵，单级反相交叉矩阵，低负载电路优化，将反馈和输出选择功能分开，限制AIC输出级数的基础上移除中间级交叉矩阵，与LUT架构进行混合等。通过大量的实验，得出针对面积延时积最优的AIC簇互连结构，与Altera公司的FPGA芯片Stratix-IV结构相比，该结构逻辑功能簇本身面积减小9.06%, MCNC应用电路集在基于优化的AIC FPGA架构上实现的平均面积延时积减小40.82%, VTR应用电路集平均面积延时积减小17.38%；与原有的AIC结构相比，簇面积减小23.16%, MCNC应用电路集平均面积延时减小27.15%, VTR应用电路集平均面积延时积减小15.26%。

Interconnect Architecture of a Novel And-inverter Cone Based FPGA Cluster

With deep understanding of the characteristics of And-Inverter Cone (AIC), an alternative logic element for FPGA, a series of improvements are proposed to get an optimized interconnect architecture inside the logic cluster. The enhancements include removing the output crossbar, adopting Inverter-Suffixed Crossbar (ISC), optimizing the low load circuit path, dividing the feedback and output function, restricting the output level of AIC and removing the middle crossbar, mixing with the LUT element. An optimized architecture is derived through amounts of experiments. Compared to Stratix IV, Altera, the area of cluster is reduced by 9.06%.Implemented on the new AIC architecture, the average area-delay product of MCNC benchmarks are reduced by 40.82%; the average area-delay product of VTR benchmarks is reduced by 17.38%. Compared to the original AIC-based FPGA architecture, the area of AIC cluster is reduced by 23.16%. Implemented on the new AIC architecture, the average area-delay product of MCNC benchmarks are reduced by 27.15%; the average area-delay product of VTR benchmarks are reduced by 15.26%.