A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs

This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 $times$ 240 pixels has been fabricated with a 0.35- $muhbox{m}$ CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 $muhbox{s}$ , which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yields DNL of $+hbox{0.53}/-!hbox{0.78}$ LSB and INL of $+hbox{1.42}/-!hbox{1.61}$ LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.