基于ZYNQ的CPFSK数字解调的设计与实现

传统数字调制解调设计采用FPGA+DSP或ADC的模式，通过传输总线完成数据的存储与传输，针对传输总线设计困难的问题，采用Xilinx新平台ZYNQ，充分利用PL部分并行运算能力强的特点完成了CPFSK解调算法IP核的设计，PS部分通过AXI总线访问IP核，传输速率高达10 Gbit·s-1，提高了对调制信号的处理速度，增加了系统的灵活性，降低了系统的体积和功耗，且便于在机载车载环境下的应用。

Design and Implementation of CPFSK Demodulation Based on ZYNQ

The traditional digital modem designed using FPGA + DSP or ADC mode performs data transmission by the bus storage and transmission. But the design of transmission bus is difficult. The new Xilinx platform ZYNQ is adopted to solve this problem. The IP core of the CPFSK demodulation algorithm is designed by taking advantage of the parallel computing capability of PL, and accessed by the PS via AXI bus at a speed of up to 10 Gbit/s, thus improving the processing speed and the flexibility of the system while reducing the system size and power consumption.