| 基于AXI4-Stream总线的数字视频接口IP核设计 |
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| 引用本文： | 郑建立,漆荣辉,张 璐.基于AXI4-Stream总线的数字视频接口IP核设计[J].电子科技,2016,29(9):161. |
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| 作者姓名： | 郑建立 漆荣辉 张 璐 |
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| 作者单位： | (上海理工大学 医疗器械与食品学院，上海 200093) |
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| 基金项目： | 上海市科委重点科技攻关基金资助项目（11441902302） |
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| 摘 要： | 针对数字视频IP核间高速流数据传输，设计并实现了一种基于AXI4-Stream总线的数字视频接口IP核，对外部输入ITU601格式的数字视频信号，将其格式转化为符合AXI4-Stream总线协议的信号，并通过IP核的主端口输出到下一级IP核的从端口。采用Xilinx ISE Design Suite 14.6软件综合设计实现，结合ISE自带ISim软件完成功能仿真，通过实际硬件电路验证了设计的正确性及可行性。
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| 关 键 词： | AXI4 Stream 数字视频信号 IP核 |
Design and Implementation of Video Interface IP Core Based on AXI4 Stream Bus |
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| ZHENG Jianli,QI Ronghui,ZHANG Lu.Design and Implementation of Video Interface IP Core Based on AXI4 Stream Bus[J].Electronic Science and Technology,2016,29(9):161. |
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| Authors: | ZHENG Jianli QI Ronghui ZHANG Lu |
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| Affiliation: | 〗(School of Medical Instrument and Food Engineering, University of Shanghai for Science and Technology, Shanghai 200093, China) |
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| Abstract: | For the high speed stream data transmission between the IP core of the digital video, we design and implement an interface IP core of the digital video based on the AXI4 Stream bus. The digital video signal from the external input in the ITU601 format is translated into the signal conforming with the bus protocol of AXI4 Stream, and then exported to the port of the next level IP core through the main port of the IP core. The accuracy and feasibility of the proposed design have been validated by the actual hardware circuit using Xilinx ISE Design Suite 14.6. |
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| Keywords: | AXI4 Stream digital video signal IP core |
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