| Abstract: | Reliability issues are important during the design of VLSI integrated circuits built on silicon, due to several design constraints-higher performance and frequency, device miniaturization, higher levels of on-chip integration-that must be satisfied by the final product. Digital designs are usually subject to failures due to the increased operating temperature caused by their high power dissipation. This paper addresses the problem of analyzing the reliability with respect to power consumption of digital systems constructed with CMOS technology. The solution is simulation-based, and relies on a new, cellular automaton-based model which is particularly suitable for identifying the power characteristics of a sequential design. The model is discussed in detail; it provides a homogeneous representation of all the components of the circuit. Primary inputs, flip-flops, primary outputs, and their related cones of combinational logic are modeled in the same way by means of cellular automaton cells. The model is used to analyze reliability of sequential VLSI circuits. To prove the applicability of the model, we report experimental results on some standard benchmarks taken from the literature |
