On the pseudo-subthreshold characteristics ofpolycrystalline-silicon thin-film transistors with large grain size |
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Authors: | Li T.-S. Lin P.-S. |
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Affiliation: | Electron. Res. & Service Organ., Ind. Technol. Res. Inst., Hsin-chu; |
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Abstract: | A two-dimensional nonplanar device simulator for polycrystalline-silicon thin-film transistors (poly-Si TFTs) was developed, in which the influence of trapped charges and carrier scattering within the grain boundary region are incorporated into Poisson's equations and drift-diffusion current formulations, respectively. With this simulator, the I-V characteristics of poly-Si TFT devices can be characterized. TFTs in polycrystalline silicon were fabricated to test the simulator. Special attention was paid to the conduction mechanism in poly-Si TFTs with large grain size. A concept called the pseudo-subthreshold region is presented to explain the observed behavior. The key factors affecting the pseudosubthreshold slope were investigated and elucidated using the simulator |
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