| 嵌入式处理器中访存部件的低功耗设计研究 |
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| 引用本文： | 黄海林,范东睿,许彤,唐志敏.嵌入式处理器中访存部件的低功耗设计研究[J].计算机学报,2006,29(5):815-821. |
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| 作者姓名： | 黄海林 范东睿 许彤 唐志敏 |
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| 作者单位： | 1. 中国科学院计算技术研究所系统结构研究室,北京,100080;中国科学院研究生院,北京,100039
2. 中国科学院计算技术研究所系统结构研究室,北京,100080 |
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| 基金项目： | 科技部科研项目;中国科学院资助项目;国家杰出青年科学基金 |
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| 摘 要： | 以“龙芯1号”处理器为研究对象,探讨了嵌入式处理器中访存部件的低功耗设计方法.通过对访存部件的结构、功耗以及关键路径进行分析,利用局部性原理,提出一种根据虚拟地址历史记录进行判断的方法,可以显著减少TLB和Cache对RAM块的访问次数,使得TLB部件功耗平均降低了28.1%,Cache部件功耗平均降低了54.3%,处理器总功耗平均降低了23.2%,而关键路径延时反而减少,处理器性能略有提高.
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| 关 键 词： | 访存部件 低功耗 龙芯1号 |
| 收稿时间： | 2005-08-01 |
| 修稿时间： | 2005-08-012006-01-11 |
Research on Low -Power Memory Hierarchy of Embedded Processor |
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| HUANG Hai-Lin,FAN Dong-Rui,XU Tong,TANG Zhi-Min.Research on Low -Power Memory Hierarchy of Embedded Processor[J].Chinese Journal of Computers,2006,29(5):815-821. |
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| Authors: | HUANG Hai-Lin FAN Dong-Rui XU Tong TANG Zhi-Min |
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| Affiliation: | 1.Computer Architecture Laboratory, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080;2.Graduate University of Chinese Academy of Sciences, Beijing 100039 |
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| Abstract: | With godson-1 processor as the research prototype, a real chip developed by ICTCAS, this paper focuses on the low-power design methodology of on-chip memory hierarchy. By analyzing the architecture, power and critical path of the memory hierarchy, a low power design meth odology based on the locality is proposed. Judging by the historical virtual memory address, the access times to TLB and Cache RAM are cut down remarkably and the power of memory hierarchy is reduced significantly. The power of TLB is reduced 28. 1% averagely, the power of Cache is reduced 54.3%averagely, and equally the power of the whole processor is reduced 23.2% averagely with some positive influence on critical path and processor performance. |
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| Keywords: | TLB Cache |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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