| 用DRAM、FPGA实现大容量FIFO存储器 |
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| 引用本文： | 孙红胜,岳春生.用DRAM、FPGA实现大容量FIFO存储器[J].信息工程大学学报,1997(3). |
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| 作者姓名： | 孙红胜 岳春生 |
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| 摘 要： | 介绍了一种实现大容量ＦＩＦＯ（ＦｉｒｓｔＩｎＦｉｒｓｔＯｕｔ）存储器的方法。采用先进的ＦＰＧＡ（ＦｉｅｌｄＰｒｏｇｒａｍｍａｂｌｅＧａｔｅＡｒａｙ）技术结合ＤＲＡＭ专用控制器件来实现控制逻辑，以动态存储器ＤＲＡＭ（ＤｙｎａｍｉｃＲＡＭ）为存储器件实现了４Ｍ字节ＦＩＦＯ。
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| 关 键 词： | DRAM，FPGA，FIFO |
The Realization of the Large Capacity FIFO Memory by Means of FPGA and DRAM |
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| Sun Hongsheng,Yue Chunsheng.The Realization of the Large Capacity FIFO Memory by Means of FPGA and DRAM[J].Journal of Information Engineering University,1997(3). |
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| Authors: | Sun Hongsheng Yue Chunsheng |
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| Affiliation: | Sun Hongsheng Yue Chunsheng |
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| Abstract: | A method of realizing the large capacity FIFO(First In First Out) memory is discussed in this article, The adoption of the advanced FPGA(Field Programmable Gate Array) technique and the special DRAM (Dynamic RAM) control device makes it possible to realize the control logic and the use of DRAM (Dynamic RAM) as the memory device helps realize the FIFO memory of 4M bytes. |
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| Keywords: | DRAM FPGA FIFO |
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