Stable high-order delta-sigma digital-to-analog converters

Stability analysis of high-order delta-sigma loops is a challenge. In this brief, a sufficient design criterion is presented for high-order multibit error-feedback digital-to-analog converters (DACs) which are especially suitable for high-speed operation. This analytical criterion might be too conservative, but it allows for the design of stable, robust, and high-resolution delta-sigma DACs. Both analytical and numerical analysis are performed for verification. Also, experimental results of a discrete-component multiplier-free prototype demonstrate 10-b operation at a very low oversampling ratio of 4.