基于多扫描链的内建自测试技术中的测试向量生成

针对基于多扫描链的内建自测试技术，提出了一种测试向量生存方法。该方法用一个线性反馈移位寄存器（LFSR）作为伪随机测试向量生成器，同时给所有扫描链输入测试向量，并通过构造具有最小相关度的多扫描链克服扫描链间的相关性对故障覆盖率的影响。此外该方法经过模拟确定难测故障集，并针对这外难测故障集利用ATPG生成最小确定性测试向量集。最后丙依据得到的最小测试向量集来设计位改变逻辑电路，利用们改变逻辑电路控制改变扫描链上特定的值来实现对难测故障的检测，从而实现被测电路和故障完全检测。

Test Pattern Generation in Built-In Self-Test with Multiple Scan Chains

Scan based built in self test (BIST), which naturally extends scan based test methodology with test patterns applied from test equipment to BIST, can be used for the self test of sequential circuits and attain higher fault coverage. If the circuit under test (CUT) contains multiple parallel scan chains, a parallel generator is needed. Known as the common pseudo random pattern generator (PRPG), an LFSR can be configured to generate a random pattern stream. The PRPG based patterns may be applied to the existing scan architecture directly from the LFSR, or through some decorrelation logic. In order to attain higher fault coverage, it is very important to analyze the test pattern generation in the scan based BIST. The paper presents a kind of scheme for test pattern generation in the scan based BIST for the circuits with multiple scan chains. In the test pattern generation scheme the PRPG, which is implemented by an LFSR, shifts the sequences into all scan chains simultaneously. The correlativity weight R(M) of multiple scan chains is also defined in the paper. Based on the analysis of the different degree effect on fault coverage due to the different configuration of multiple scan chains, one conclusion is drawn that the probability that the fault coverage is reduced is increased with an increase of the correlativity weight R(M) . If the circuit is tested by the multiple scan chains with the minimum R(M) , the probability that the fault coverage is reduced is least. In the paper a method to construct multiple scan chains with minimum correlativity weight R(M) is proposed to overcome the bad effect on fault coverage due to the correlation between scan chains. Furthermore the minimum set of deterministic patterns is generated for hard to test faults by ATPG and the set is used to design the bit modifying logic circuit (BML), which is located between multiple scan chains and the CUT. Through BML the signals in multiple scan chains are controlled to input to the CUT. When the test control signal is low, the test patterns in multiple scan chains are input into the CUT directly. When the test control signal is high, the value of the signals at certain bit positions in the multiple scan chains are modified by BML and the changed test patterns are input into the CUT to test hard to test faults for complete fault coverage. The experiments on some ISCAS'89 benchmark circuits show that the complete fault coverage can be obtained by the test method presented by the paper. The overhead of BML is also analyzed.